1. Field of the Invention
The present invention relates to a clock supplying apparatus and a control method thereof, and more particularly, to a clock supplying apparatus and a control method that are suitable to supply a clock signal to a semiconductor integrated circuit or other circuit blocks.
2. Description of the Related Art
In recent years, semiconductor integrated circuits such as ASICs (Application Specified ICs) have become large in scale, and with their increasing scale, they are generally designed as clock synchronous circuits. Besides, there is an increasing demand for low power LSI chips that are low in power consumption. To meet the demand, gated clock circuits capable of stopping, as required, clock signal supply to circuit blocks are realized to reduce the power consumption (refer to Japanese Laid-open Patent Publication (Kokai) No. H10-308450).
More specifically, the conventional ASIC includes flip-flops for individually controlling the drive of circuit blocks in the ASIC, and a free-run clock signal is always supplied to all the flip-flops. As a result, even if one or more circuit blocks are not driven due to for example that they are in a waiting mode, all the flip-flops for the circuit blocks are always ON/OFF operated (toggle operated), resulting in wasted power consumption.
In addition, recent ASICs are designed to be driven at high speed to conform to the increase in circuit scale and clock signal frequency, and thus their power consumption is large. Therefore, a reduction in power consumption has been demanded.
It has also been known to use the ASIC for image processing in information processing apparatuses, which include digital copying machines, multifunction peripherals with scanner, printer and FAX functions, and cellular phones. These machines and apparatuses are generally held for a long period of time in a waiting mode that is comprised of various waiting states. In a multifunction peripheral for example, there are various waiting modes such as a waiting state where the FAX function is ON and the printer and scanner functions are OFF, and another waiting state where the FAX and printer functions are ON and the scanner function is OFF.
The gated clock circuit is very useful to reduce power consumption in these waiting states. Specifically, the gated clock circuit can stop the clock signal supply to flip-flops in a circuit block that is functionally OFF, thereby stopping the toggle operation of the flip-flops for reduction of power consumption. Thus, especially in the information processing apparatuses which can have a long waiting time period, a considerable reduction in power consumption can be realized by using the ASIC installed with the gated clock circuit.
However, in an ASIC with plural function blocks, when a certain function block is stopped operating by means of the gated clock system, the toggle operation (ON/OFF operation) of flip-flops of the stopped function block is abruptly stopped. As a result, the consumption current in the stopped function block abruptly decreases, but the power consumption of the entire ASIC does not decrease abruptly, resulting in increase in bias voltages supplied to the other function blocks. When any of the increasing bias voltages exceeds the rated voltage of the ASIC, there will be an erroneous operation or hung-up (locked state) of the ASIC.
When the operation of a certain function block is started by means of the gated clock system, flip-flops of the started function block abruptly starts the toggle operation (ON/OFF operation). This causes an abrupt increase in the consumption current in the started function block, but the power consumption in the entire ASIC does not increase, which results in decrease in bias voltages applied to the other function blocks. When any of the decreasing bias voltages is less than the rated ASIC voltage, there will be an erroneous operation or hung-up (locked state) of the ASIC.
To obviate this, a technique is used of inserting a capacitor between the power supply line and the ground line for the ASIC, to thereby suppress an abrupt change in power source line voltage.
With the speeding up of clock signal and increase in circuit scale in recent ASICs, however, a large current fluctuation can be caused even in the case where the gated clock technique is applied, making it difficult to suppress the current fluctuation by the capacitor insertion technique.
In addition, there is a demand for further improving the response of the power supply circuit for the ASIC to the current fluctuation, which results in increased costs.